open_project floyd_warshall
set_top kernel_floyd_warshall
add_files floyd_warshall.cpp
add_files -tb "floyd_warshall_tb.cpp check.data"
open_solution solution1
set_part xc7z010clg400-1
create_clock -period 10 -name default
csim_design
csynth_design
cosim_design
exit
